I. Field of the Invention
The invention relates to a frequency divider device, a method for dividing the frequency of a signal, a frequency generator device and a method for generating a frequency. The invention further relates to electronic devices, e.g. a receiver device, a transmitter device, a transceiver device or a phase locked loop including a frequency divider device according to the invention.
II. Related Art and Other Considerations
In the art, frequency dividers are generally known. Frequency dividers are used in numerous types of devices, for example in Phase Locked Loop (ILL) circuits. PLL circuits are used for example as integrated synthesisers which generate and define local oscillator signals in receivers, transmitters and transceivers (combined receivers and transmitters).
It is known in the art to implement frequency dividers with latches or flip-flops. The division ratio is then an integer, i.e. 2, 3, 4, 5 etc.
For realising non-integer division ratios, like for instance 2.34567, a fractional divider is known in the art. A fractional divider multiplies the incoming frequency with a first integer number N and divides this signal by a second integer number M. For suitable combinations of N and M, this results in a non-integer division ratio since the (long-term averaged) division ratio is N/M. Another option for realising a non-integer division ratio is known in the art by implementing a delta-sigma divider. The delta-sigma divider is rapidly switched between different division ratios, whereby as an average the desired fractional division ratio is obtained.
However, the known frequency dividers are disadvantageous since in PLL circuits several opposing requirements have to be met. For example, the characteristics of a PLL circuit may be described in terms of bandwidth: a large PLL-bandwidth results in a relatively short lock-in time. In a PLL circuit having a large PLL bandwidth, the noise of the voltage controlled oscillator (VCO) inside the loop-bandwidth will also be relatively low. The phase-detector, apart from generating a DC component for controlling the VCO, also generates a spurious component at twice the reference frequency. A low-pass filter has to attenuate this component sufficiently in order to obtain a spurious-free output signal. The PLL-bandwidth may be limited by the required attenuation of these spurious components. A high reference frequency is thus desirable. However, in a frequency divider having an integer division ratio the frequency step, that is the difference in frequency between one division ratio (e.g. N) and a next division ratio (N+1), equals the reference frequency. The requirements relating to the optimal characteristics like PLL-bandwidth, phase-noise, frequency step and lock-in time are thus conflicting requirements.
Furthermore, in the known fractional divider the output signal of the divider has a significant amount of jitter (as seen in the time domain) or spurious frequency components (as seen in the frequency domain). If such a fractional divider is used in a PLL the jitter or the spurious frequencies again require a compromise between the PLL-bandwidth, phase noise, frequency step and lock-in time specifications.
In a delta-sigma divider the rapid switching between different division ratios generates a lot of (random) spurious frequency components in the signal. Even though said spurious components may be located outside the PLL-bandwidth, this again requires a compromise between PLL-bandwidth and dithering-noise requirements.